The present invention relates to semiconductor devices with accurately formed sub-micron features. The present invention has particular applicability in fabricating high density semiconductor devices with reduced series resistance.
As integrated circuit geometries continue to plunge into the deep sub-micron regime, it becomes increasingly more difficult to accurately form discreet devices on a semiconductor substrate exhibiting the requisite reliability and circuit operating speed. High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance (R) and capacitance (C) of the interconnection system. The higher the value of the Rxc3x97C product, the more limiting the circuit operating speed. Miniaturization requires long interconnects having small contacts and small cross-sections. Accordingly, continuing reduction in design rules into the deep sub-micron regime requires decreasing the R and C associated with interconnection paths. Thus, low resistivity interconnection paths are critical to fabricating dense, high performance devices.
A common approach to reduce the resistivity of the interconnect to less than that exhibited by polysilicon alone comprises forming a multilayer structure consisting of a low resistance material, e.g., a refractory metal silicide, on a doped polycrystalline silicon layer, typically referred to as a polycide. Advantageously, the polycide gate/interconnect structure preserves the known work function of polycrystalline silicon and the highly reliable polycrystalline silicon/silicon oxide interface, since polycrystalline silicon is directly on the gate oxide.
Implementation of salicide technology as device dimensions plunge generates various issues, notably dopant deactivation. Dopant deactivation is particularly acute at the interface between the metal silicide layers formed on the semiconductor substrate and the underlying silicon. The contact resistance at the silicon/metal silicide interface is a large component of the overall series resistance. Implementation of silicidation at elevated temperatures reduces the dopant concentration at the interface which is manifested by a high resistance.
Accordingly, there exists a need for methodology enabling the fabrication of semiconductor devices comprising transistors with improved series resistance and a significant reduction in dopant deactivation at the interface between metal silicide layers and substrate silicon.
An advantage of the present invention is a method of manufacturing a semiconductor device comprising transistors with reduced series resistance and high dopant concentration at the interface between metal silicide layers and underlying silicon in the substrate.
Another advantage of the present invention is a semiconductor device comprising transistors with reduced series resistance and high dopant concentration at the interface between metal silicide layers and substrate silicon.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present 8invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a gate electrode over a main surface of a substrate with a gate dielectric layer therebetween, the gate electrode having an upper surface and side surfaces; forming shallow source/drain extensions in the substrate; forming dielectric sidewall spacers on the side surfaces of the gate electrode; forming first metal silicide layers on the main surface of the substrate adjacent dielectric sidewall spacers and a second metal silicide layer on the upper surface of the gate electrode; forming deep source/drain implants in the substrate under the first metal silicide layers; and laser thermal annealing to activate deep source/drain regions.
Another aspect of the present invention is a semiconductor device comprising: a gate electrode, having an upper surface and side surfaces, over a main surface of the substrate with a gate dielectric layer therebetween; dielectric sidewall spacers on the side surfaces of the gate electrode; shallow source/drain extensions in the substrate under the dielectric sidewall spacers; metal silicide layers on the main surface of the substrate adjacent the dielectric sidewall spacers; and deep source/drain regions extending into the substrate under the metal silicide layers, the deep source/drain regions having an upper portion with a first impurity concentration adjacent the metal silicide layers and a lower portion with a second impurity concentration, less than the first impurity concentration, extending below the upper portion.
Embodiments of the present invention comprise forming preamorphized regions extending into the substrate to a first depth below the first metal silicide layers and ion planting to form the deep source/drain implants overlapping the preamorphized regions to a second depth below the first metal silicide layers greater than the first depth. Embodiments of the present invention include forming the preamorphized regions at a first depth from the main surface of the substrate of 800 xc3x85 to 1,800 xc3x85, and forming the deep source/drain implants at a second depth from the main surface of the substrate of 1,000 xc3x85 to 2,000 xc3x85. Embodiments of the present invention further include laser thermal annealing by impinging a pulsed laser light beam at a radiant fluence of 0.2 to 0.8 joules/cm2 for 1 to 10 nanoseconds. The resulting deep source/drain regions have an upper portion at an interface with the metal silicide layers with an impurity concentration greater than that of a lower portion extending deeper into the substrate.
Additional advantages of the present invention will be readily apparent to those skilled in the art from the following detailed description wherein the embodiments of the present invention are described simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.